The present application is a continuation application of PCT/JP01/02985 filed on Apr. 6, 2001, claiming priority from a Japanese patent application No. 2000-106443 filed on Apr. 7, 2000, the contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a delay circuit and a ring oscillator.
2. Description of the Related Art
FIG. 1 is a block diagram of a conventional variable delay circuit 10. The conventional variable delay circuit 10 includes an input terminal 12, a coarse delay circuit 14, a fine delay circuit 16, memories 18 and 20 which store data for controlling the coarse delay circuit 14 and the fine delay circuit 16 respectively, and an output terminal 22. The coarse delay circuit 14 generates a long span of coarse delay, and the fine delay circuit 16 generates a short span of fine delay.
FIG. 2 shows a configuration of the coarse delay circuit 14 included in the conventional variable delay circuit 10. FIG. 2A shows the coarse delay circuit 14 in which (nxe2x88x921) stages of buffers are connected by cascade connection. Input of the buffer of the first stage and output of the buffers of each stage connect to a selector 30. The selector 30 selects one of n signal lines based on a supplied control signal CTRL. The coarse delay circuit 14 shown in FIG. 2A has coarse delay resolution equivalent to one buffer, i.e., resolution equivalent to two inverters.
FIG. 2B shows the coarse delay circuit 14 constituted by a plurality of NAND circuits. In this coarse delay circuit 14, an input signal diverges to n stages of paths, and is supplied to NAND circuits respectively. Control signals CTRL (1)-(n) are supplied to the NAND circuits positioned at the first stage of each path respectively. The plurality of NAND circuits are positioned at n stages of paths so that the coarse delay circuit 14 has coarse delay resolution equivalent to two NAND circuits.
FIG. 3 shows the configuration of the fine delay circuit 16 included in the conventional variable delay circuit 10. FIG. 3A shows the fine delay circuit 16 in which a plurality of capacitors, constituted from transfer gates 32 and gates 34 of transistors, connect to a signal line in parallel. Control signals are supplied to each of the transfer gates 32, and they perform on-off control independently. By varying the number of the transfer gates 32 which are turned on, a plurality of stages of capacitors are utilized as a variable capacitor. The fine delay circuit 16 generates a short fine delay by curving a rise/fall edge of a waveform using the variable capacitor.
FIG. 3B shows the fine delay circuit 16 in which a plurality of stages of transistors 36 are inserted in the power supply section of an inverter. Control signals are supplied to gates of each of the transistors 36, which perform on-off control independently. By varying the number of the gates which are turned on, the plurality of stages of transistors are utilized as a variable resistance. The fine delay circuit 16 generates a short fine delay by varying a time constant for charging a load capacitance of the inverter using this variable resistance.
Since the conventional variable delay circuit 10 shown in FIG. 1 has two stages of delay circuits in which the coarse delay circuit 14 and the fine delay circuit 16 are connected in series, a size of the circuit becomes large. Consequently, in the variable delay circuit 10, there is a problem that the variable delay circuit 10 requires a measurable amount of power, and there is a strong possibility of deteriorating an accuracy of delay span. Furthermore, there is a drawback that the coarse delay circuit 14 shown in FIG. 2A has a long offset propagation delay time (tPD). Moreover, the coarse delay circuit 14 shown in FIG. 2B and the fine delay circuit 16 shown in FIGS. 3A and B have a drawback that input loads of delay elements are not uniform.
FIG. 4 is a diagram for explaining a consumed electric current wave of a circuit in which a plurality of buffers are connected by cascade connection. FIG. 4A shows a consumed electric current wave when input loads of buffers are uniform. In this case, it is shown that the wave of the consumed electric current is flat. FIG. 4B shows a consumed electric current wave when input loads of buffer are not uniform. A circuit, in which a capacitor is positioned between some buffers, is shown as an example. When a signal is supplied to this circuit, the wave of the consumed electric current cannot be maintained to be flat since a capacitor performs charge and discharge, which causes a supply current to be fluctuated. The noise which appears in the consumed electric current wave has a bad influence on other circuits in the variable delay circuit 10, and especially this noise easily fluctuates an operating characteristic of a circuit which has long rise/fall time. For this reason, there has been a problem that it is difficult to generate a accurate delay span using the coarse delay circuit 14 shown in FIG. 2B and the fine delay circuit 16 shown in FIGS. 3A and B.
Accordingly, it is an object of the present invention to provide a delay circuit which solve the foregoing problem and a ring oscillator which includes the delay circuit. The object can be achieved by combinations described in the independent claims. The dependent claims define further advantageous and exemplary combinations of the present invention.
In order to solve the foregoing problem, the first aspect of the present invention provides a delay circuit which delays an input signal. The delay circuit includes an input terminal to which the input signal is supplied, a plurality of delay paths which have a plurality of delay elements and are connected in parallel to the input terminal, and a connection path which connects electrically an output of a delay element in a first delay path in the plurality of delay paths, and an input of a delay element in a second delay path which is different from the first delay path. This delay circuit may include a connection path which connects electrically an output of a delay element in the second delay path, and an input of a delay element in the first delay path.
The delay circuit in the first aspect may further include at least one connection path which connects electrically an output of the delay element in at least one delay path among the plurality of delay paths, and an input of the delay element in another delay path which is positioned at a following stage of the delay path, and a connection path which connects electrically an output of the delay element in a delay path of an final stage, and an input of the delay element in a delay path of a first stage. At this time, it is preferable that the plurality of connection paths connect the delay paths from the first stage to the final stage in order, and to connect the delay path of the final stage and the first stage.
The delay element may also include a logic gate circuit which has at least two inputs, a first input and a second input. Moreover, all the delay elements may be constituted by the logic gate circuits. It is preferable that the logic gate circuit in the delay path makes either the first input or the second input to be an input to the logic gate circuit based on a desired delay span which delays the input signal. Moreover, the logic gate circuit may be a NAND circuit.
Moreover, an additional element maybe positioned at an input of the predetermined delay element so that input loads of the delay elements may be substantially equalized. It is preferable that the additional element is the same element as the delay element. When the delay element is constituted by a logic gate circuit, it is preferable that the additional element is also constituted by a logic gate circuit. Moreover, the connection path may include the delay element. Moreover, the logic gate circuit maybe a NAND circuit.
The second aspect of the present invention provides a delay circuit which delays an input signal. The delay circuit includes an input terminal to which the input signal is supplied, a delay path which has a plurality of delay elements and connects to the input terminal, and an additional element positioned at an input of the predetermined delay element so that input loads of the delay elements in the delay paths may be substantially equalized. It is preferable that the additional element is the same element as the delay element.
The third aspect of the present invention provides a ring oscillator which varies an oscillation frequency. The ring oscillator includes a delay path which has a plurality of delay elements, a feedback line which returns an output of the delay path to an input of the delay path, and an additional element positioned at an input of the predetermined delay element so that input loads of the delay elements in the delay paths may be substantially equalized. It is preferable that the additional element is the same element as the delay element. Moreover, it is preferable that the ring oscillator has the plurality of delay paths connected in parallel, and a connection path which connects electrically an output of the delay element in a first delay path among the plurality of delay paths and an input of the delay element in a second delay path which is different from the first delay path.
This summary of invention does not necessarily describe all necessary features so that the invention may also be a sub-combination of these described features.